(a) Field of the Invention
The present invention relates to a computer system having a ROM correction unit and, more particularly, to a ROM correction unit for use in a computer system operating with a pipe-line processing based on a program stored in a ROM.
(b) Description of the Related Art
Single-chip microcomputer systems running on programs stored in mask ROMs are increasingly used for a variety of applications. In the single-chip microcomputer system, even if a bug is found in the program stored in the mask ROM, the bug cannot be eliminated from the then-existing microcomputer system. Thus, a ROM correction technique is proposed wherein the original instruction group in a program having a bug therein is replaced by a modified instruction group free from the bug. The replacement of the instruction group is generally conducted at the stage when the CPU finds the top address (or subject address) of the original instruction group to be replaced with the modified instruction group.
Patent Publication JP-A-8-95946 describes a microcomputer system having a ROM correction function, such as shown in FIG. 1. The microcomputer system 93 includes a pipe-line processing CPU 87 having an instruction queue therein, a register 86 for storing the subject address of the original instruction group in the program having a bug therein, a RAM 84 for storing a top address (or branch address) of a modified instruction group, a fetch pointer 81 for counting and indicating the current address of the instruction to be fetched by the instruction queue, a comparator 85 for comparing the address in the fetch pointer 81 against the subject address stored in the register 86 to deliver a coincidence signal (selection signal) 92, a branch-instruction output unit 89 for delivering a branch instruction signal for indicating a jump to the branch address of the modified instruction group, and a selector 88 for selecting the current address for the ROM 83 or the branch instruction signal supplied from the branch-instruction output unit 89 based on the coincidence signal.
The selector 88 delivers the branch instruction signal to the CPU 87 at the stage of the fetch of the address if the comparator 85 finds a coincidence therein. Thus, the CPU 87 bypasses the original instruction group having the bug and operates instead on the modified instruction group supplied from the RAM 84.
In the proposed ROM correction technique, the subject address of the original instruction group having a bug therein is set in the register 86 before the CPU 87 operates on the program.
If a plurality of bugs are found in the separate portions of the program stored in the mask ROM 83, the ROM correction technique must indicate the priority order among the plurality of subject addresses, and the CPU 87 must correctly judge the priority order, which requires a complicated procedure however.
In view of the above, it is an object of the present invention to provide a computer system having a ROM correction unit therein and operating with pipe-line processing, which is capable of correctly recognizing operation of the ROM correction unit and thus recognize the priority order if a plurality of ROM correction units are provided in the computer system.
The present invention provides a computer system including a CPU for operating with pipe-line processing, a ROM storing a program to be executed by the CPU, and at least one ROM correction unit including a first storage unit for storing a subject address of an original instruction group in the program having a bug therein, a second storage unit for storing a modified instruction group for replacing the original instruction group by the modified instruction group having a branch address, a comparator for comparing a current address of a current instruction read from the ROM against the subject address, a selector for selecting the current address or the branch address based on a result of the comparison by the comparator, and a flag generator for setting a ROM correction flag when the selector selects the branch address.
In accordance with the computer system of the present invention, since the flag generator of the ROM correction unit informs the CPU the operation of the ROM correction unit, the CPU correctly recognizes operation of the ROM correction unit. Thus, if a plurality of ROM correction units are provided in the computer system, the CPU correctly recognizes the priority order of the ROM correction units, whereby a plurality of original instruction groups in a program stored in a ROM can be replaced by respective modified instruction groups.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.